vishay siliconix sir474dp document number: 68996 s-82749-rev. a, 10-nov-08 www.vishay.com 1 n-channel 30-v (d-s) mosfet features ? halogen-free ? trenchfet ? power mosfet ? low thermal resistance powerpak ? package with low 1.07 mm profile ? optimized for high-side synchronous rectifier operation ? 100 % r g tested ? 100 % uis tested applications ? notebook cpu core - high-side sw itch product summary v ds (v) r ds(on) ( ) i d (a) a, g q g (typ.) 30 0.0095 at v gs = 10 v 20 8 nc 0.012 at v gs = 4.5 v 20 ordering information: SIR474DP-T1-GE3 (lead (pb)-free and halogen-free) 1 2 3 4 5 6 7 8 s s s g d d d d 6.15 mm 5.15 mm powerpak so-8 bottom view n-channel mosfet g d s notes: a. base on t c = 25 c. b. surface mounted on 1" x 1" fr4 board. c. t = 10 s. d. see solder profile ( h ttp://www.vishay.com/ppg?73257 ). the powerpak so-8 is a leadless pack age. the end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. a solder fillet at the exposed copper tip cannot b e guaranteed and is not required to ensure adequate bottom side solder interconnection. e. rework conditions: manual soldering with a sol dering iron is not recommended for leadless components. f. maximum under steady state conditions is 70 c/w. g. packaged limited. absolute maximum ratings t a = 25 c, unless otherwise noted parameter symbol limit unit drain-source voltage v ds 30 v gate-source voltage v gs 20 continuous drain current (t j = 150 c) t c = 25 c i d 20 g a t c = 70 c 20 g t a = 25 c 15 b, c t a = 70 c 12 b, c pulsed drain current i dm 50 continuous source-drain diode current t c = 25 c i s 20 g t a = 25 c 3.2 b, c single pulse avalanche current l = 0.1 mh i as 20 avalanche energy e as 20 mj maximum power dissipation t c = 25 c p d 29.8 w t c = 70 c 19.0 t a = 25 c 3.9 b, c t a = 70 c 2.5 b, c operating junction and storage temperature range t j , t stg - 55 to 150 c soldering recommendations (peak temperature) d, e 260 thermal resistance ratings parameter symbol typical maximum unit maximum junction-to-ambient b, f t 10 s r thja 27 32 c/w maximum junction-to-case (drain) steady state r thjc 3.5 4.2
www.vishay.com 2 document number: 68996 s-82749-rev. a, 10-nov-08 vishay siliconix sir474dp notes: a. pulse test; pulse width 300 s, duty cycle 2 %. b. guaranteed by design, not s ubject to production testing. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. specifications t j = 25 c, unless otherwise noted parameter symbol test conditions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = 250 a 30 v v ds temperature coefficient v ds /t j i d = 250 a 34 mv/c v gs(th) temperature coefficient v gs(th) /t j - 4.7 gate-source threshold voltage v gs(th) v ds = v gs , i d = 250 a 1.0 2.2 v gate-source leakage i gss v ds = 0 v, v gs = 20 v 100 na zero gate voltage drain current i dss v ds = 30 v, v gs = 0 v 1 a v ds = 30 v, v gs = 0 v, t j = 55 c 10 on-state drain current a i d(on) v ds 5 v, v gs = 10 v 30 a drain-source on-state resistance a r ds(on) v gs = 10 v, i d = 10 a 0.0075 0.0095 v gs = 4.5 v, i d = 7 a 0.010 0.012 forward transconductance a g fs v ds = 15 v, i d = 10 a 30 s dynamic b input capacitance c iss v ds = 15 v, v gs = 0 v, f = 1 mhz 985 pf output capacitance c oss 205 reverse transfer capacitance c rss 76 total gate charge q g v ds = 15 v, v gs = 10 v, i d = 10 a 18 27 nc v ds = 15 v, v gs = 4.5 v, i d = 10 a 812 gate-source charge q gs 2.4 gate-drain charge q gd 2.3 gate resistance r g f = 1 mhz 0.3 1.3 2.6 tu r n - o n d e l ay t i m e t d(on) v dd = 15 v, r l = 1.5 i d ? 10 a, v gen = 4.5 v, r g = 1 14 25 ns rise time t r 12 24 turn-off delay time t d(off) 19 35 fall time t f 918 tu r n - o n d e l ay t i m e t d(on) v dd = 15 v, r l = 1.5 i d ? 10 a, v gen = 10 v, r g = 1 816 rise time t r 10 20 turn-off delay time t d(off) 16 30 fall time t f 918 drain-source body diode characteristics continuous source-drain diode current i s t c = 25 c 20 a pulse diode forward current a i sm 50 body diode voltage v sd i s = 3 a 0.76 1.1 v body diode reverse recovery time t rr i f = 10 a, di/dt = 100 a/s, t j = 25 c 14 28 ns body diode reverse recovery charge q rr 510nc reverse recovery fall time t a 8 ns reverse recovery rise time t b 6
document number: 68996 s-82749-rev. a, 10-nov-08 www.vishay.com 3 vishay siliconix sir474dp typical characteristics 25 c, unless otherwise noted output characteristics on-resistance vs. drain current and gate voltage gate charge 0 10 20 30 40 50 0.0 0.5 1.0 1.5 2.0 2.5 v gs =10thr u 4 v v gs =3 v v ds - drain-to-so u rce v oltage ( v ) - drain c u rrent (a) i d 0.005 0.007 0.009 0.011 0.013 0.015 0 1020304050 v gs =10 v v gs =4.5 v - on-resistance ( ) r ds(on) i d - drain c u rrent (a) 0 2 4 6 8 10 0.0 3.7 7.4 11.1 14. 8 1 8 .5 v ds =20 v i d =10a v ds =15 v v ds =10 v - gate-to-so u rce v oltage ( v ) q g - total gate charge (nc) v gs transfer characteristics capacitance on-resistance vs. junction temperature 0.0 1.6 3.2 4. 8 6.4 8 .0 012345 t c = 25 c t c = 125 c t c = - 55 c v gs - gate-to-so u rce v oltage ( v ) - drain c u rrent (a) i d c rss 0 260 520 7 8 0 1040 1300 0.0 2.4 4. 8 7.2 9.6 12.0 c iss c oss v ds - drain-to-so u rce v oltage ( v ) c - capacitance (pf) 0.6 0. 8 1.0 1.2 1.4 1.6 1. 8 - 50 - 25 0 25 50 75 100 125 150 i d =10a v gs =4.5 v v gs =10 v t j -j u nction temperat u re (c) ( n ormalized) - on-resistance r ds(on)
www.vishay.com 4 document number: 68996 s-82749-rev. a, 10-nov-08 vishay siliconix sir474dp typical characteristics 25 c, unless otherwise noted source-drain diode forward voltage threshold voltage 0.0 0.2 0.4 0.6 0. 8 1.0 1.2 1 0.01 0.001 0.1 10 100 t j = 150 c t j = 25 c v sd -so u rce-to-drain v oltage ( v ) - so u rce c u rrent (a) i s - 0. 8 - 0.6 - 0.4 - 0.2 0.0 0.2 0.4 - 50 - 25 0 25 50 75 100 125 150 i d = 250 a i d =5ma v ariance ( v ) v gs(th) t j - temperat u re (c) on-resistance vs. gate-to-source voltage single pulse power, junction-to-ambient 0.00 0.01 0.02 0.03 0.04 0.05 01234567 8 910 t j = 25 c t j = 125 c - on-resistance ( ) r ds(on) v gs - gate-to-so u rce v oltage ( v ) 0 16 32 4 8 64 8 0 0 1 1 1 0 0 . 00.01 time (s) po w er ( w ) 0.1 safe operating area, junction-to-ambient 100 1 0.1 1 10 100 0.01 10 0.1 t a =25 c single p u lse 1s 10 s limited b yr ds(on) * b v dss limited 1ms 10 ms 100 ms dc v ds - drain-to-so u rce v oltage ( v ) * v gs > minim u m v gs at w hich r ds(on) is specified - drain c u rrent (a) i d
document number: 68996 s-82749-rev. a, 10-nov-08 www.vishay.com 5 vishay siliconix sir474dp typical characteristics 25 c, unless otherwise noted * the power dissipation p d is based on t j(max) = 150 c, using junction-to-case thermal resi stance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. it is used to determ ine the current rating, when this rating falls below the package limit. current derating* 0.0 9.2 1 8 .4 27.6 36. 8 46.0 0 255075100125150 package limited t c - case temperat u re (c) i d - drain c u rrent (a) power derating, junction-to-case 0.0 7.2 14.4 21.6 2 8 . 8 36.0 0 25 50 75 100 125 150 t c - case temperat u re (c) po w er ( w ) power derating, junction-to-ambient 0.00 0.44 0. 88 1.32 1.76 2.20 0 25 50 75 100 125 150 t a -am b ient temperat u re (c) po w er ( w )
www.vishay.com 6 document number: 68996 s-82749-rev. a, 10-nov-08 vishay siliconix sir474dp typical characteristics 25 c, unless otherwise noted vishay siliconix maintains worldwide manufacturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?68996. normalized thermal transient im pedance, junction-to-ambient 0.2 0.1 t 1 t 2 n otes: p dm 1. d u ty cycle, d = 2. per unit base = r thja = 70 c/ w 3. t jm -- t a =p dm z thja (t) t 1 t 2 4. s u rface mo u nted d u ty cycle = 0.5 single p u lse 0.02 0.05 10 -3 10 -2 1 10 1000 10 -1 10 -4 100 s qu are w a v ep u lse d u ration (s) n ormalized effecti v e transient thermal impedance 0.1 0.01 1 normalized thermal transient impedance, junction-to-case 10 -3 10 -2 0 1 1 10 -1 10 -4 0.2 0.1 d u ty cycle = 0.5 s qu are w a v ep u lse d u ration (s) n ormalized effecti v e transient thermal impedance 1 0.1 0.01 0.05 0.02 single p u lse
package information www.vishay.com vishay siliconix revison: 20-may-13 1 document number: 71655 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 powerpak ? so-8, (single/dual) millimeters inches dim. min. nom. max. min. nom. max. a 0.97 1.04 1.12 0.038 0.041 0.044 a1 - 0.05 0 - 0.002 b 0.33 0.41 0.51 0.013 0.016 0.020 c 0.23 0.28 0.33 0.009 0.011 0.013 d 5.05 5.15 5.26 0.199 0.203 0.207 d1 4.80 4.90 5.00 0.189 0.193 0.197 d2 3.56 3.76 3.91 0.140 0.148 0.154 d3 1.32 1.50 1.68 0.052 0.059 0.066 d4 0.57 typ. 0.0225 typ. d5 3.98 typ. 0.157 typ. e 6.05 6.15 6.25 0.238 0.242 0.246 e1 5.79 5.89 5.99 0.228 0.232 0.236 e2 (for al product) 3.30 3.48 3.66 0.130 0.137 0.144 e2 (for other product) 3.48 3.66 3.84 0.137 0.144 0.151 e3 3.68 3.78 3.91 0.145 0.149 0.154 e4 (for al product) 0.58 typ. 0.023 typ. e4 (for other prod uct) 0.75 typ. 0.030 typ. e 1.27 bsc 0.050 bsc k (for al product) 1.45 typ. 0.057 typ. k (for other produc t) 1.27 typ. 0.050 typ. k1 0.56 - - 0.022 - - h 0.51 0.61 0.71 0.020 0.024 0.028 l 0.51 0.61 0.71 0.020 0.024 0.028 l1 0.06 0.13 0.20 0.002 0.005 0.008 ? 0 - 12 0 - 12 w 0.15 0.25 0.36 0.006 0.010 0.014 m 0.125 typ. 0.005 typ. ecn: c13-0702-rev. k, 20-may-13 dwg: 5881 3. dimensions exclusive of mold flash and cutting burrs. 1. notes 2 inch will govern. dimensions exclusive of mold gate burrs. backside view of single pad backside view of dual pad detail z d d1 d2 c a e1 d1 e2 d2 e b 1 2 3 4 h 4 3 2 1 1 2 3 4 b l d2 d3 (2x) z a1 k1 k d e w l1 d5 e3 d4 e4 e4 k l h e2 d4 d5 m e3 2 2
application note 826 vishay siliconix document number: 72599 www.vishay.com revision: 21-jan-08 15 application note recommended minimum pads for powerpak ? so-8 single 0.174 (4.42) recommended mi nimum pads dimensions in inches/(mm) 0.260 (6.61) 0.024 (0.61) 0.154 (3.91) 0.150 (3.81) 0.050 (1.27) 0.050 (1.27) 0.032 (0.82) 0.040 (1.02) 0.026 (0.66) return to index return to index
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